Metal-Oxide-Semiconductor (MOS) electrically programmable read-only memories (EPROMS) frequently use memory cells that have electrically isolated gates (floating gates). These floating gates are typically completely surrounded by insulation and formed from a polycrystalline silicon (polysilicon) layer. Information is stored in the memory cells or devices in the form of charge on the floating gates. Charge is transported to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc., depending upon the construction of the cells. The cells are erased generally by exposing the array to ultraviolet radiation. An example of these cells can be found in U.S. Pat. Nos. 3,500,142; 3,660,819; 3,755,721; and 4,099,196. In some cases these cells are electrically erasable (EEPROM) cells. An example of such a cell is shown in U.S. Pat. No. 4,203,158.
The invention of the present application is used with an EPROM cell, particularly one which is electrically erasable, commonly referred to as a "flash" EPROM cell.
Due to the nature and design of a typical flash memory device, the entire device must be erased in order to erase any one cell in that device. Flash memory array blocking allows segregating different portions or types of data. In this way, when one portion needs to be erased, the other portion(s) do not have to be erased.
However, whenever any cells in a given block are programmed, even cells in another block may be affected by such effects as slow programming due to the combination of potentials necessarily applied to the cells.
Prior attempts at controlling these combination of potentials have met with limited success and have revealed such effects as slow erasing, again due to the combination of potentials then applied to the cells.
Proper control of all of the potentials applied to all of the cells in all of the blocks of a flash memory array, as discussed herein, substantially eliminates the problems of both slow programming and slow erasing.